Hardware Conscious Architecture Search Algorithms for Specialized AI Accelerators

Abstract

Deep neural networks have become a growing trend in artificial intelligence, and their energy-efficient, high-performance capabilities require specialized AI accelerators. But traditional neural architecture search approaches focus on prediction issues without considering practical hardware factors like latency, memory bandwidth, and power consumption.  Therefore, this study proposes a hardware-in-the-loop neural architecture co-design framework that integrates accelerator-aware feedback directly into the optimization process. This approach integrates the reinforcement learning-driven architecture search with a cycle-accurate hardware simulator in order to optimize both the neural network architecture and hardware execution approaches. The method uses a hardware-aware cost function that relies on the Energy-Delay Product metric to effectively explore energy-efficient and latency-aware neural architectures. Experimentation confirmed that the proposed methodology attained a classification accuracy rate of 94.3%, which is significantly better than the FLOPS-based approach with an accuracy rate of 91.2%. Moreover, its inference time was reduced from 23.4ms to 14.7ms, and its energy usage was decreased from 8.1mJ to 5.4mJ. The optimized methodology further increased power efficiency by 58.1%, minimizing the EDP to 79.4 mJ·ms. Therefore, this research study demonstrates that hardware-aware co-design is an effective solution for designing AI models that are efficient in deployment.